One approach to achieving sub-10 nm geometry devices would co-integrate Si/Ge (SixGe1-x where x=0 to 1) with a Group III-V compound semiconductor material (hybrid Group III-V and SiGe). The Group III-V material could be a binary material such, as for example, Gallium Arsenide (GaAs) or Gallium Antimonide (GaSb). The Group III-V material could also be a tertiary material such as, for example, Indium Gallium Arsenide (InGaAs) or Indium Gallium Antimonide (InGaSb).
Wafer bonding could be used to achieve the co-integration of the Si/Ge with the Group III-V material in order to form dual channel substrates. Since bonding two such dissimilar materials is performed via two wafer bonding, it implies that the channels will not be at the same height and thus the device gates formed on the Group III-V channels and the SiGe channels will not be at the same height. This variation in wafer topography can be problematic when performing chemical-mechanical polish (CMP) and other processing steps, especially for replacement gate processing where a gate precursor structure (sometimes referred to as ‘dummy’ gate structure), needs to be subsequently removed and replaced with a metal gate (stack) and associated gate dielectric.